1. Field of the Invention
This invention relates to a surface-normal optoelectronic device to be used for highly parallel optical transmission and optical information processing or the like.
2. Description of the Prior Art
Such a surface-normal optoelectronic device that the input and output of light can be made in the direction perpendicular to the surface of a semiconductor substrate and that possesses a latch function is an indispensable key device to be used for computer-to-computer data transmission and optical computing. A conventional surface-normal optoelectronic device is cross-sectionally shown in FIG. 1. This device is disclosed in the Japanese Laid-Open Patent Publication No. 64-14963.
The conventional surface-normal optoelectronic device shown in FIG. 1 has a so-called pnpn structure, in which on an n-type GaAs substrate 60, an n-type A1GaAs layer 61 (A1 composition ratio 0.4; layer thickness 1 .mu.m; doping concentration of donor 1.times.10.sup.18 cm.sup.-3) , a p-type GaAs layer 62 (layer thickness 50 .ANG.; doping concentration of acceptor 1.times.10.sup.19 cm.sup.-3), an n-type GaAs layer 63 (layer thickness 1 .mu.m; doping concentration of donor 1.times.10.sup.17 cm.sup.-3), a p-type A1GaAs layer 64 (A1 composition ratio 0.4; layer thickness 0.5 .mu.m; doping concentration of acceptor 1.times.10.sup.18 cm.sup.-3), and a p-type GaAs layer 65 (layer thickness 0.15 .mu.m; doping concentration of acceptor 1.times.10.sup.19 cm.sup.-3) are laminatedly formed in this order. The n-type GaAs layer 60 and n-type A1GaAs layer 61 constitute a cathode region, the p-type GaAs layer 62 constitutes a p-type gate region, the n-type GaAs layer 63 constitutes an n-type gate region, the p-type A1GaAs layer 64 constitutes an anode region, and the p-type GaAs layer 65 constitutes a contact layer.
The GaAs substrate 60 has a cathode electrode 66 of an AuGe--Ni alloy formed on the lower surface opposite to the surface on which the n-type A1GaAs layer 61 is formed, and on the upper surface of the p-type GaAs layer 65, an anode electrode 67 of an Au--Cr--AuZn alloy is formed. In addition, a p-type diffusion region 68 is provided so as to pass from the upper surface of the n-type GaAs layer 63 through the n-type GaAs layer 63 and p-type GaAs layer 62 to the n-type A1GaAs layer 61. In the area just above the p-type diffusion region 68 on the upper surface of the n-type GaAs layer 63, an n-type gate electrode 69 of an Au--Cr--AuZn alloy is formed, and a p-type gate electrode 70 of an AuGe--Ni alloy is formed on the upper surface of the n-type GaAs layer 63 on the opposite side to the n-type gate electrode 69 with respect to a mesa portion formed on the surface of the n-type GaAs layer 63.
In case of using the above-mentioned conventional surface-normal optoelectronic device, a bias voltage is applied between the anode and cathode electrodes 67 and 66 so as to make the anode electrode 67 positive and the cathode electrode 66 negative, and the value of this bias voltage is set to a value just before the device is turned on. At this time, a voltage is not applied to the n-type gate electrode 69 and p-type gate electrode 70. Next, when a trigger light is applied to the n-type gate electrode 69 or the p-type gate electrode 70, the device is turned on to emit light as shown in FIG. 1. When once turned on, it is maintained even if the trigger light is stopped being applied. In this case, if the p-type A1GaAs layer 64 constituting the anode region, n-type A1GaAs layer 61 constituting the cathode region and n-type GaAs substrate 60 are made larger in forbidden band width than the p-type GaAs layer 62 constituting the p-type gate electrode and n-type GaAs layer 63 constituting the n-type gate electrode, carriers are confined into these gate regions, resulting in an enhancement in luminous efficiency. In order to turn it off, the polarity of the bias voltage applied to the anode electrode 67 and the cathode electrode 66 is reversed, and further, a voltage is applied so as to make the n-type gate electrode 66 positive and the p-type gate electrode 70 negative. As a result, the carriers confined into these gate regions shown above are forcibly taken out of the device, so that it is turned off. This means that high speed turn-off operation becomes possible.
With the conventional surface-normal optoelectronic device as shown in FIG. 1, light emission occurs in the light emitting diode (LED) mode under the turned-on condition, but it is unsatisfactory in its electro-optic conversion efficiency. In addition, the turn-off time is as large as several hundreds psec, so that more rapid response time is desirable. Further, because the gate electrodes 69 and 70 are provided, an electric current flows expandingly not only through a range corresponding to a light emitting portion (mesa portion) of the p-type GaAs layer 62 as an active layer but also through a range outside of this range, which means that satisfactory luminous efficiency cannot be obtained. Also, the spontaneous emission mode has a limitation upon frequency characteristic, thus rendering it impossible to operate at high speed.
Therefore, an object of this invention is to provide a surface-normal optoelectronic device which makes it possible to perform turn-on and turn-off operations at higher speed than would be provided by the above-described conventional surface-normal optoelectronic device as well as to obtain higher luminous efficiency.
Another object of this invention is to provide a surface-normal optoelectronic device which is operable in a laser diode (LD) mode superior in electro-optic conversion efficiency.